1. Field of Invention
The present invention generally relates to a method and system of calibrating the control delay time, and more particularly, to a calibration method and system used to define the effective retrieved range of the control delay time to obtain the optimal control delay time when the control chip is performing the reading operation.
2. Description of Related Art
Since the development of the data processing speed for the currently used personal computer is getting faster and faster, the requirement of the efficiency and accuracy for accessing the data stored in memory needs to be relatively improved, so as to effectively adapt with the data processing speed of the personal computer CPU. Therefore, how to assure the accuracy of the data read from memory when the control chip performs the memory read operation becomes a very important subject.
The method for the control chip (e.g. north bridge chip) to access memory uses the data strobe signal (acronym as DQS hereinafter) after an appropriate delay to latch the memory data signal. For the Double Data Rate Synchronous Dynamic Random Access Memory (acronym as DDR SDRAM), a quarter cycle control delay time is provided. Generally speaking, the control delay time in the control chip is determined by a set control delay value, and the control delay time can be changed by modifying the magnitude of the control delay value. Moreover, the control chip used currently is set by the BIOS based on the default values when the system is initialized only one time, and the default values are set based on the data sheet provided by the control chip vendor. Since the default values cannot be adjusted according to factors such as the individual environment, element status or the circuit layout, the control delay time is not located at the optimal position, so factors that make the system unstable increase.
The more advanced control chips used currently can estimate the initial control delay value from the loop, and the value can compensate for the impact due to manufacture factor of the whole system. However, under the circumstance where the clock cycle gets higher, the accuracy and the reliability of the control delay time obtained by using such a method gets lower and lower.